HLASM Miscellaneous Info

Assembler instruction statements are divided into three groups:
     Machine Instructions are translated into machine executable code.
     Assembler Instructions are directives to the assembler program.
     Macro Instructions are expanded during preassembly into machine and assembler instructions.

A symbol is defined by the name field of an instruction.  It may contain a relocatable value for the address of a machine instruction or storage location, or an absolute value assigned by an EQU statement.

The location counter is the offset from the beginning of the control section of each instruction.  It is adjusted for boundary alignment just before an instruction is assembled, then it is incremented by the instruction’s length.

The assembler compiles a symbol table with an entry for each symbol, containing its location counter value, its length, and other attribures.

The location counter reference is the term (*) which resolves, during assembly, to the relocatable address of the first byte of the instruction containing it.  The symbol length attribute reference is the term (L'symbol) which resolves, during assembly, to the length attribute of a symbol’s entry in the symbol table.  The term (L'*) resolves to the length of the instruction containing it.

*                                                  FLDB INTO FLDA
LOOP     B     *                         INFINITE LOOP
LOOP2    B     *+L'*-4                   SAME LOOP - BC INSTR LEN = 4
LOADA    L     R5,=A(*)                  ADDR OF LOADA -> R5
LOADB    LA    R5,LOADB                  SAME FOR LOADB
         DC    A(L'*+3)                  ASSEMBLES TO X'00000007'
SPACE    DC    X'40'                     FW ALIGNED BY LAST CONST
AFTSPACE EQU   *                         EQUALS SPACE+1
FW       DS    F                         FW ALIGNED

The value of a location counter reference that occurs in an address constant containing a field of multiple nominal values depends upon whether the definition of the address constant is a DC instruction or a literal.  A DC instruction occurs at a fixed location within the control section; therefore, the value of the location counter reference depends upon the position within the field of multiple nominal values of the one in which it occurs.  But, a literal address constant occurs at a location that depends upon the composition and placement of the literal pool; therefore, the value of the location counter reference is defined as the address of the first byte of the instruction containing the literal, regardless of the position of the nominal value in which it occurs.

ADCONS   DC    A(108,*+4096,HDR)         VALUE OF * = ADCONS+4
LOADLIT  LM    R4,R6,=A(108,*+4096,HDR)  VALUE OF * = LOADLIT

The LTORG instruction designates the starting location of the literal pool which by default would fall at the end of the first CSECT.  Placing the literal pool before I/O areas prevents possible overlay of literals.

Note the following techniques:

DECR     BCTR  R5,0                      DECREMENT R5
COMPUTE  LA    R5,10(R3,R4)              R5 = R3 + R4 + 10

Paired symbols resolve to an absolute value at assembly time since both symbols must reside in the same control section and their offsets therein are fixed.  Paired explicit-format relocatable addresses do not qualify.  For example, the following attempt to index an SS-format instruction by converting the index register to a displacement will not assemble:

         AP    SALARY+(0(R5)-0(0)),=P'5000'

An SS-format operand assembles to one register, one absolute displacement, and one absolute length.

In an instruction operand that specifies a single register to represent a pair of consecutive registers, coding an even-numbered register designates an even-odd pair.  Coding an odd-numbered register designates only that single register, in instructions that allow it.  Under this scheme, the 16 general registers are divided into 8 even-odd pairs.

To load the numeric value of a literal to a register, code the storage operand of the Load Address (LA) instruction as an absolute number no larger than 12 bits.  This assembles the storage operand with a displacement of the number and a zero base and index register.

         LA   R8,123                    LOAD DECIMAL 123 TO R8
         LA   R8,123(0,0)               SAME AS ABOVE

An RX-format instruction coded with a single register and no leading comma assembles the storage operand with a zero base register.

         BAL   R12,AROUND(R15)          NO BASE REGISTER
         BAL   R12,AROUND(0,R15)        SAME EFFECT AS ABOVE

Note how the absence of the comma affects the object code in the following:


000004 45CF 0058            00058     8          BAL   R12,AROUND(R15)

000004 45C0 F058            00058     8          BAL   R12,AROUND(,R15)

The effect of either statement is the same, but the first statement, which lacks a leading comma, places R15 into the first halfword as the index register and places 0 into the second halfword as the base register.  The presence of an index register degrades performance.

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